// SPDX-License-Identifier: CERN-OHL-S-2.0

// A basic valid-ready ram, default 16KiB

`default_nettype none
`timescale 1ps/1ps

module uart 
( 
    input logic     clk_i,
    input logic     rst_ni,

    input logic     uart_i,
    output logic    uart_o
);

    // TODO: implement
    
endmodule