# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select -global-isel-abort=1 %s | FileCheck %s
--- |
  define i32 @jt_test(i32 %x) {
  entry:
    switch i32 %x, label %return [
      i32 75, label %sw.bb
      i32 34, label %sw.bb
      i32 56, label %sw.bb
      i32 35, label %sw.bb
      i32 40, label %sw.bb
      i32 4, label %sw.bb1
      i32 5, label %sw.bb1
      i32 6, label %sw.bb1
    ]

  sw.bb:
    %add = add nsw i32 %x, 42
    br label %return

  sw.bb1:
    %mul = mul nsw i32 %x, 3
    br label %return

  return:
    %retval.0 = phi i32 [ %mul, %sw.bb1 ], [ %add, %sw.bb ], [ 0, %entry ]
    ret i32 %retval.0
  }

...
---
name:            jt_test
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
jumpTable:
  kind:            block-address
  entries:
    - id:              0
      blocks:          [ '%bb.3', '%bb.3', '%bb.3', '%bb.4', '%bb.4', '%bb.4',
                         '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
                         '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
                         '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
                         '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
                         '%bb.2', '%bb.2', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
                         '%bb.2', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
                         '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
                         '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.2', '%bb.4',
                         '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
                         '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
                         '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.2' ]
body:             |
  ; CHECK-LABEL: name: jt_test
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   successors: %bb.4(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $w0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
  ; CHECK-NEXT:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def $nzcv
  ; CHECK-NEXT:   [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[SUBSWri]], %subreg.sub_32
  ; CHECK-NEXT:   [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 71, 0, implicit-def $nzcv
  ; CHECK-NEXT:   Bcc 8, %bb.4, implicit $nzcv
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1.entry:
  ; CHECK-NEXT:   successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
  ; CHECK-NEXT:   [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
  ; CHECK-NEXT:   early-clobber %17:gpr64, early-clobber %18:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
  ; CHECK-NEXT:   BR %17
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2.sw.bb:
  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[ADDWri:%[0-9]+]]:gpr32sp = nsw ADDWri [[COPY]], 42, 0
  ; CHECK-NEXT:   B %bb.4
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3.sw.bb1:
  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
  ; CHECK-NEXT:   [[MADDWrrr:%[0-9]+]]:gpr32 = nsw MADDWrrr [[COPY]], [[MOVi32imm]], $wzr
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.4.return:
  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32 = PHI [[MADDWrrr]], %bb.3, [[ADDWri]], %bb.2, [[COPY1]], %bb.0, [[COPY2]], %bb.1
  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.1.entry:
    liveins: $w0

    %0:gpr(s32) = COPY $w0
    %4:gpr(s32) = G_CONSTANT i32 71
    %8:gpr(s32) = G_CONSTANT i32 3
    %10:gpr(s32) = G_CONSTANT i32 42
    %13:gpr(s32) = G_CONSTANT i32 0
    %1:gpr(s32) = G_CONSTANT i32 4
    %2:gpr(s32) = G_SUB %0, %1
    %3:gpr(s64) = G_ZEXT %2(s32)
    %5:gpr(s64) = G_ZEXT %4(s32)
    %14:gpr(s32) = G_ICMP intpred(ugt), %3(s64), %5
    G_BRCOND %14, %bb.4

  bb.5.entry:
    successors: %bb.3, %bb.4, %bb.2

    %17:gpr(s32) = G_CONSTANT i32 0
    %7:gpr(p0) = G_JUMP_TABLE %jump-table.0
    G_BRJT %7(p0), %jump-table.0, %3(s64)

  bb.2.sw.bb:
    %16:gpr(s32) = G_CONSTANT i32 42
    %11:gpr(s32) = nsw G_ADD %0, %16
    G_BR %bb.4

  bb.3.sw.bb1:
    %15:gpr(s32) = G_CONSTANT i32 3
    %9:gpr(s32) = nsw G_MUL %0, %15

  bb.4.return:
    %12:gpr(s32) = G_PHI %9(s32), %bb.3, %11(s32), %bb.2, %13(s32), %bb.1, %17(s32), %bb.5
    $w0 = COPY %12(s32)
    RET_ReallyLR implicit $w0

...