# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select -mattr=-fullfp16 -global-isel %s -o - | FileCheck %s
...
---
name: test_f16.rint
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $h0
; CHECK-LABEL: name: test_f16.rint
; CHECK: liveins: $h0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
; CHECK-NEXT: %1:fpr32 = nofpexcept FCVTSHr [[COPY]]
; CHECK-NEXT: %2:fpr32 = nofpexcept FRINTXSr %1
; CHECK-NEXT: %3:fpr16 = nofpexcept FCVTHSr %2
; CHECK-NEXT: $h0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $h0
%0:fpr(s16) = COPY $h0
%2:fpr(s32) = G_FPEXT %0(s16)
%3:fpr(s32) = G_FRINT %2
%1:fpr(s16) = G_FPTRUNC %3(s32)
$h0 = COPY %1(s16)
RET_ReallyLR implicit $h0
...
---
name: test_v4f16.rint
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_v4f16.rint
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub
; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG1]], 2
; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG2]], 3
; CHECK-NEXT: %5:fpr32 = nofpexcept FCVTSHr [[COPY1]]
; CHECK-NEXT: %6:fpr32 = nofpexcept FRINTXSr %5
; CHECK-NEXT: %7:fpr16 = nofpexcept FCVTHSr %6
; CHECK-NEXT: %8:fpr32 = nofpexcept FCVTSHr [[DUPi16_]]
; CHECK-NEXT: %9:fpr32 = nofpexcept FRINTXSr %8
; CHECK-NEXT: %10:fpr16 = nofpexcept FCVTHSr %9
; CHECK-NEXT: %11:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]]
; CHECK-NEXT: %12:fpr32 = nofpexcept FRINTXSr %11
; CHECK-NEXT: %13:fpr16 = nofpexcept FCVTHSr %12
; CHECK-NEXT: %14:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]]
; CHECK-NEXT: %15:fpr32 = nofpexcept FRINTXSr %14
; CHECK-NEXT: %16:fpr16 = nofpexcept FCVTHSr %15
; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], %7, %subreg.hsub
; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], %10, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 0
; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], %13, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG5]], 0
; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], %16, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG6]], 0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub
; CHECK-NEXT: $d0 = COPY [[COPY2]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
%2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
%16:fpr(s32) = G_FPEXT %2(s16)
%17:fpr(s32) = G_FRINT %16
%6:fpr(s16) = G_FPTRUNC %17(s32)
%14:fpr(s32) = G_FPEXT %3(s16)
%15:fpr(s32) = G_FRINT %14
%7:fpr(s16) = G_FPTRUNC %15(s32)
%12:fpr(s32) = G_FPEXT %4(s16)
%13:fpr(s32) = G_FRINT %12
%8:fpr(s16) = G_FPTRUNC %13(s32)
%10:fpr(s32) = G_FPEXT %5(s16)
%11:fpr(s32) = G_FRINT %10
%9:fpr(s16) = G_FPTRUNC %11(s32)
%1:fpr(<4 x s16>) = G_BUILD_VECTOR %6(s16), %7(s16), %8(s16), %9(s16)
$d0 = COPY %1(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: test_v8f16.rint
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v8f16.rint
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 2
; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 3
; CHECK-NEXT: [[DUPi16_3:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 4
; CHECK-NEXT: [[DUPi16_4:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 5
; CHECK-NEXT: [[DUPi16_5:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 6
; CHECK-NEXT: [[DUPi16_6:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 7
; CHECK-NEXT: %9:fpr32 = nofpexcept FCVTSHr [[COPY1]]
; CHECK-NEXT: %10:fpr32 = nofpexcept FRINTXSr %9
; CHECK-NEXT: %11:fpr16 = nofpexcept FCVTHSr %10
; CHECK-NEXT: %12:fpr32 = nofpexcept FCVTSHr [[DUPi16_]]
; CHECK-NEXT: %13:fpr32 = nofpexcept FRINTXSr %12
; CHECK-NEXT: %14:fpr16 = nofpexcept FCVTHSr %13
; CHECK-NEXT: %15:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]]
; CHECK-NEXT: %16:fpr32 = nofpexcept FRINTXSr %15
; CHECK-NEXT: %17:fpr16 = nofpexcept FCVTHSr %16
; CHECK-NEXT: %18:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]]
; CHECK-NEXT: %19:fpr32 = nofpexcept FRINTXSr %18
; CHECK-NEXT: %20:fpr16 = nofpexcept FCVTHSr %19
; CHECK-NEXT: %21:fpr32 = nofpexcept FCVTSHr [[DUPi16_3]]
; CHECK-NEXT: %22:fpr32 = nofpexcept FRINTXSr %21
; CHECK-NEXT: %23:fpr16 = nofpexcept FCVTHSr %22
; CHECK-NEXT: %24:fpr32 = nofpexcept FCVTSHr [[DUPi16_4]]
; CHECK-NEXT: %25:fpr32 = nofpexcept FRINTXSr %24
; CHECK-NEXT: %26:fpr16 = nofpexcept FCVTHSr %25
; CHECK-NEXT: %27:fpr32 = nofpexcept FCVTSHr [[DUPi16_5]]
; CHECK-NEXT: %28:fpr32 = nofpexcept FRINTXSr %27
; CHECK-NEXT: %29:fpr16 = nofpexcept FCVTHSr %28
; CHECK-NEXT: %30:fpr32 = nofpexcept FCVTSHr [[DUPi16_6]]
; CHECK-NEXT: %31:fpr32 = nofpexcept FRINTXSr %30
; CHECK-NEXT: %32:fpr16 = nofpexcept FCVTHSr %31
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %11, %subreg.hsub
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], %14, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], %17, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG2]], 0
; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], %20, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG3]], 0
; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], %23, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane3:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane2]], 4, [[INSERT_SUBREG4]], 0
; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], %26, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane4:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane3]], 5, [[INSERT_SUBREG5]], 0
; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], %29, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane5:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane4]], 6, [[INSERT_SUBREG6]], 0
; CHECK-NEXT: [[DEF7:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], %32, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi16lane6]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<8 x s16>) = COPY $q0
%2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16) = G_UNMERGE_VALUES %0(<8 x s16>)
%32:fpr(s32) = G_FPEXT %2(s16)
%33:fpr(s32) = G_FRINT %32
%10:fpr(s16) = G_FPTRUNC %33(s32)
%30:fpr(s32) = G_FPEXT %3(s16)
%31:fpr(s32) = G_FRINT %30
%11:fpr(s16) = G_FPTRUNC %31(s32)
%28:fpr(s32) = G_FPEXT %4(s16)
%29:fpr(s32) = G_FRINT %28
%12:fpr(s16) = G_FPTRUNC %29(s32)
%26:fpr(s32) = G_FPEXT %5(s16)
%27:fpr(s32) = G_FRINT %26
%13:fpr(s16) = G_FPTRUNC %27(s32)
%24:fpr(s32) = G_FPEXT %6(s16)
%25:fpr(s32) = G_FRINT %24
%14:fpr(s16) = G_FPTRUNC %25(s32)
%22:fpr(s32) = G_FPEXT %7(s16)
%23:fpr(s32) = G_FRINT %22
%15:fpr(s16) = G_FPTRUNC %23(s32)
%20:fpr(s32) = G_FPEXT %8(s16)
%21:fpr(s32) = G_FRINT %20
%16:fpr(s16) = G_FPTRUNC %21(s32)
%18:fpr(s32) = G_FPEXT %9(s16)
%19:fpr(s32) = G_FRINT %18
%17:fpr(s16) = G_FPTRUNC %19(s32)
%1:fpr(<8 x s16>) = G_BUILD_VECTOR %10(s16), %11(s16), %12(s16), %13(s16), %14(s16), %15(s16), %16(s16), %17(s16)
$q0 = COPY %1(<8 x s16>)
RET_ReallyLR implicit $q0