# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s

---
name:            add_lhs_sub_reg
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: add_lhs_sub_reg
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
    %0:_(s32) = COPY $w0
    %1:_(s32) = COPY $w1
    %2:_(s32) = G_SUB %0, %1
    %3:_(s32) = G_ADD %2, %1
    $w0 = COPY %3
...
---
name:            add_lhs_sub_reg_wide
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0, $q1
    ; CHECK-LABEL: name: add_lhs_sub_reg_wide
    ; CHECK: liveins: $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
    ; CHECK-NEXT: $q0 = COPY [[COPY]](s128)
    %0:_(s128) = COPY $q0
    %1:_(s128) = COPY $q1
    %2:_(s128) = G_SUB %0, %1
    %3:_(s128) = G_ADD %2, %1
    $q0 = COPY %3
...
---
name:            add_lhs_sub_reg_vec
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $x0, $x1
    ; CHECK-LABEL: name: add_lhs_sub_reg_vec
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $x0
    ; CHECK-NEXT: $x0 = COPY [[COPY]](<4 x s16>)
    %0:_(<4 x s16>) = COPY $x0
    %1:_(<4 x s16>) = COPY $x1
    %2:_(<4 x s16>) = G_SUB %0, %1
    %3:_(<4 x s16>) = G_ADD %2, %1
    $x0 = COPY %3
...
---
name:            add_rhs_sub_reg
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: add_rhs_sub_reg
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
    %0:_(s32) = COPY $w0
    %1:_(s32) = COPY $w1
    %2:_(s32) = G_SUB %0, %1
    %3:_(s32) = G_ADD %1, %2
    $w0 = COPY %3
...
---
name:            add_rhs_sub_reg_wide
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0, $q1
    ; CHECK-LABEL: name: add_rhs_sub_reg_wide
    ; CHECK: liveins: $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
    ; CHECK-NEXT: $q0 = COPY [[COPY]](s128)
    %0:_(s128) = COPY $q0
    %1:_(s128) = COPY $q1
    %2:_(s128) = G_SUB %0, %1
    %3:_(s128) = G_ADD %1, %2
    $q0 = COPY %3
...
---
name:            add_rhs_sub_reg_vec
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $x0, $x1
    ; CHECK-LABEL: name: add_rhs_sub_reg_vec
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $x0
    ; CHECK-NEXT: $x0 = COPY [[COPY]](<4 x s16>)
    %0:_(<4 x s16>) = COPY $x0
    %1:_(<4 x s16>) = COPY $x1
    %2:_(<4 x s16>) = G_SUB %0, %1
    %3:_(<4 x s16>) = G_ADD %1, %2
    $x0 = COPY %3
...