# REQUIRES: amdgpu-registered-target
# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir --delta-passes=register-uses -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t

# CHECK-INTERESTINGNESS: V_MUL_F32_e32 %vgpr0
# CHECK-INTERESTINGNESS: V_MUL_F32_e32 {{.*}}%vgpr1, %vgpr0

# CHECK-INTERESTINGNESS: SI_CALL {{.*}}$vgpr0
# CHECK-INTERESTINGNESS: SI_CALL {{.*}}$vgpr3


# RESULT: %mul0:vgpr_32 = V_MUL_F32_e32 %vgpr0, undef %vgpr1, implicit $mode, implicit $exec
# RESULT: %mul1:vgpr_32 = V_MUL_F32_e32 undef %vgpr1, %vgpr0, implicit $mode, implicit $exec
# RESULT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
# RESULT: $vgpr1 = V_MOV_B32_e32 1, implicit $exec
# RESULT: $sgpr30_sgpr31 = SI_CALL undef %call_target, @callee, csr_amdgpu, implicit $vgpr0
# RESULT: $sgpr30_sgpr31 = SI_CALL undef %call_target, @callee, csr_amdgpu, implicit $vgpr3
# RESULT: %impdef:vreg_64 = IMPLICIT_DEF
# RESULT: GLOBAL_STORE_DWORD undef %ptr, undef %impdef.sub1, 0, 0, implicit $exec
# RESULT: undef %impdef.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
# RESULT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
# RESULT: S_BARRIER
# RESULT: S_ENDPGM 0

--- |
  define void @func()  {
    ret void
  }

  declare void @callee()
...

---
name: func
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1

    S_WAITCNT 0
    %vgpr0:vgpr_32 = COPY $vgpr0
    %vgpr1:vgpr_32 = COPY $vgpr1
    %mul0:vgpr_32 = V_MUL_F32_e32 %vgpr0, %vgpr1, implicit $mode, implicit $exec
    %mul1:vgpr_32 = V_MUL_F32_e32 %vgpr1, %vgpr0, implicit $mode, implicit $exec
    %call_target:sreg_64 = IMPLICIT_DEF
    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    $vgpr1 = V_MOV_B32_e32 1, implicit $exec
    $sgpr30_sgpr31 = SI_CALL %call_target, @callee, csr_amdgpu, implicit $vgpr0, implicit $vgpr1
    $vgpr2 = V_MOV_B32_e32 2, implicit $exec
    $vgpr3 = V_MOV_B32_e32 3, implicit $exec
    $sgpr30_sgpr31 = SI_CALL %call_target, @callee, csr_amdgpu, implicit $vgpr2, implicit $vgpr3
    %impdef:vreg_64 = IMPLICIT_DEF
    %ptr:vreg_64 = IMPLICIT_DEF
    GLOBAL_STORE_DWORD %ptr, %impdef.sub1, 0, 0, implicit $exec
    %impdef.sub0 = V_MOV_B32_e32 0, implicit $exec
    $scc = IMPLICIT_DEF
    S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.1:
    S_BARRIER
    S_ENDPGM 0, implicit %mul0, implicit %mul1
...